//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/* Copyright 2001 Intel Corp.  */
/*++

Module Name:  $Workfile: BVD_UDC_Bits.h $

Abstract:
  Contains macro definitions for the USB Device Controller
  Registers bit manipulation

Functions:


Notes:

--*/

#ifndef __UDCBITS_H__
#define __UDCBITS_H__


// Masks for UDC Registers

// UDC Control Register (UDCCR)
#define XLLP_UDC_UDCCR_UDE          ( 0x1U << 0 )	// UDC enabled
#define XLLP_UDC_UDCCR_UDA			( 0x1U << 1 )	// READ-ONLY: udc is active
#define XLLP_UDC_UDCCR_UDR			( 0x1U << 2 )	// Forces the usb out of suspend state
#define XLLP_UDC_UDCCR_EMCE			( 0x1U << 3 )	// The Endpoint memory config. has an error
#define XLLP_UDC_UDCCR_SMAC			( 0x1U << 4 )	// Switch Endpoint memory to Active config.
                                                    // Active interface and Alternate Interface
#define XLLP_UDC_UDCCR_AAISN_SHIFT  5               // Shift and a mask for the Alternate Interface
#define XLLP_UDC_UDCCR_AAISN_MASK   ( 0x7U << XLLP_UDC_UDCCR_AAISN_SHIFT )  // Settings  (0-7)
#define XLLP_UDC_UDCCR_AIN_SHIFT    8               // Shift and a mask for the Interface
#define XLLP_UDC_UDCCR_AIN_MASK     ( 0x7U << XLLP_UDC_UDCCR_AIN_SHIFT )    // Number    (0-7)
#define XLLP_UDC_UDCCR_ACN_SHIFT    11              // Shift and a mask for the Configuration
#define XLLP_UDC_UDCCR_ACN_MASK     ( 0x3U << XLLP_UDC_UDCCR_ACN_SHIFT )    // Number    (0-3)
#define XLLP_UDC_UDCCR_DRWF			( 0x1U << 16 )	// Device Remote Wakeup Feature

// UDC Interrupt Control Register 0 (UDCICR0)
#define XLLP_UDC_UDCICR0_IE0_0		( 0x1U << 0 )	// Packet Complete Interrupt Enable - Endpoint 0
#define XLLP_UDC_UDCICR0_IE0_1		( 0x1U << 1 )   // FIFO Error Interrupt Enable - Endpoint 0
#define XLLP_UDC_UDCICR0_IEA_0		( 0x1U << 2 )	// Packet Complete Interrupt Enable - Endpoint A
#define XLLP_UDC_UDCICR0_IEA_1		( 0x1U << 3 )   // FIFO Error Interrupt Enable - Endpoint A
#define XLLP_UDC_UDCICR0_IEB_0		( 0x1U << 4 )	// Packet Complete Interrupt Enable - Endpoint B
#define XLLP_UDC_UDCICR0_IEB_1		( 0x1U << 5 )   // FIFO Error Interrupt Enable - Endpoint B
#define XLLP_UDC_UDCICR0_IEC_0		( 0x1U << 6 )	// Packet Complete Interrupt Enable - Endpoint C
#define XLLP_UDC_UDCICR0_IEC_1		( 0x1U << 7 )   // FIFO Error Interrupt Enable - Endpoint C
#define XLLP_UDC_UDCICR0_IED_0		( 0x1U << 8 )	// Packet Complete Interrupt Enable - Endpoint D
#define XLLP_UDC_UDCICR0_IED_1		( 0x1U << 9 )   // FIFO Error Interrupt Enable - Endpoint D
#define XLLP_UDC_UDCICR0_IEE_0		( 0x1U << 10 )	// Packet Complete Interrupt Enable - Endpoint E
#define XLLP_UDC_UDCICR0_IEE_1		( 0x1U << 11 )  // FIFO Error Interrupt Enable - Endpoint E
#define XLLP_UDC_UDCICR0_IEF_0		( 0x1U << 12 )	// Packet Complete Interrupt Enable - Endpoint F
#define XLLP_UDC_UDCICR0_IEF_1		( 0x1U << 13 )  // FIFO Error Interrupt Enable - Endpoint F
#define XLLP_UDC_UDCICR0_IEG_0		( 0x1U << 14 )	// Packet Complete Interrupt Enable - Endpoint G
#define XLLP_UDC_UDCICR0_IEG_1		( 0x1U << 15 )  // FIFO Error Interrupt Enable - Endpoint G
#define XLLP_UDC_UDCICR0_IEH_0		( 0x1U << 16 )	// Packet Complete Interrupt Enable - Endpoint H
#define XLLP_UDC_UDCICR0_IEH_1		( 0x1U << 17 )  // FIFO Error Interrupt Enable - Endpoint H
#define XLLP_UDC_UDCICR0_IEI_0		( 0x1U << 18 )	// Packet Complete Interrupt Enable - Endpoint I
#define XLLP_UDC_UDCICR0_IEI_1		( 0x1U << 19 )  // FIFO Error Interrupt Enable - Endpoint I
#define XLLP_UDC_UDCICR0_IEJ_0		( 0x1U << 20 )	// Packet Complete Interrupt Enable - Endpoint J
#define XLLP_UDC_UDCICR0_IEJ_1		( 0x1U << 21 )  // FIFO Error Interrupt Enable - Endpoint J
#define XLLP_UDC_UDCICR0_IEK_0		( 0x1U << 22 )	// Packet Complete Interrupt Enable - Endpoint K
#define XLLP_UDC_UDCICR0_IEK_1		( 0x1U << 23 )  // FIFO Error Interrupt Enable - Endpoint K
#define XLLP_UDC_UDCICR0_IEL_0		( 0x1U << 24 )	// Packet Complete Interrupt Enable - Endpoint L
#define XLLP_UDC_UDCICR0_IEL_1		( 0x1U << 25 )  // FIFO Error Interrupt Enable - Endpoint L
#define XLLP_UDC_UDCICR0_IEM_0		( 0x1U << 26 )	// Packet Complete Interrupt Enable - Endpoint M
#define XLLP_UDC_UDCICR0_IEM_1		( 0x1U << 27 )  // FIFO Error Interrupt Enable - Endpoint M
#define XLLP_UDC_UDCICR0_IEN_0		( 0x1U << 28 )	// Packet Complete Interrupt Enable - Endpoint N
#define XLLP_UDC_UDCICR0_IEN_1		( 0x1U << 29 )  // FIFO Error Interrupt Enable - Endpoint N
#define XLLP_UDC_UDCICR0_IEP_0		( 0x1U << 30 )	// Packet Complete Interrupt Enable - Endpoint P
#define XLLP_UDC_UDCICR0_IEP_1		( 0x1U << 31 )  // FIFO Error Interrupt Enable - Endpoint P

#define XLLP_UDC_UDCICR0_ENABLE_ALL 0xFFFFFFFE      // Mask to enable all endpoint A - P interrupts

// UDC Interrupt Control Register 1 (UDCICR1)
#define XLLP_UDC_UDCICR1_IEQ_0		( 0x1U << 0 )	// Packet Complete Interrupt Enable - Endpoint Q
#define XLLP_UDC_UDCICR1_IEQ_1		( 0x1U << 1 )   // FIFO Error Interrupt Enable - Endpoint Q
#define XLLP_UDC_UDCICR1_IER_0		( 0x1U << 2 )	// Packet Complete Interrupt Enable - Endpoint R
#define XLLP_UDC_UDCICR1_IER_1		( 0x1U << 3 )   // FIFO Error Interrupt Enable - Endpoint R
#define XLLP_UDC_UDCICR1_IES_0		( 0x1U << 4 )	// Packet Complete Interrupt Enable - Endpoint S
#define XLLP_UDC_UDCICR1_IES_1		( 0x1U << 5 )   // FIFO Error Interrupt Enable - Endpoint S
#define XLLP_UDC_UDCICR1_IET_0		( 0x1U << 6 )	// Packet Complete Interrupt Enable - Endpoint T
#define XLLP_UDC_UDCICR1_IET_1		( 0x1U << 7 )   // FIFO Error Interrupt Enable - Endpoint T
#define XLLP_UDC_UDCICR1_IEU_0		( 0x1U << 8 )	// Packet Complete Interrupt Enable - Endpoint U
#define XLLP_UDC_UDCICR1_IEU_1		( 0x1U << 9 )   // FIFO Error Interrupt Enable - Endpoint U
#define XLLP_UDC_UDCICR1_IEV_0		( 0x1U << 10 )	// Packet Complete Interrupt Enable - Endpoint V
#define XLLP_UDC_UDCICR1_IEV_1		( 0x1U << 11 )  // FIFO Error Interrupt Enable - Endpoint V
#define XLLP_UDC_UDCICR1_IEW_0		( 0x1U << 12 )	// Packet Complete Interrupt Enable - Endpoint W
#define XLLP_UDC_UDCICR1_IEW_1		( 0x1U << 13 )  // FIFO Error Interrupt Enable - Endpoint W
#define XLLP_UDC_UDCICR1_IEX_0		( 0x1U << 14 )	// Packet Complete Interrupt Enable - Endpoint X
#define XLLP_UDC_UDCICR1_IEX_1		( 0x1U << 15 )  // FIFO Error Interrupt Enable - Endpoint X
#define XLLP_UDC_UDCICR1_IERS		( 0x1U << 27 )  // Interrupt Enable - Reset
#define XLLP_UDC_UDCICR1_IESU		( 0x1U << 28 )  // Interrupt Enable - Suspend
#define XLLP_UDC_UDCICR1_IERU		( 0x1U << 29 )  // Interrupt Enable - Resume
#define XLLP_UDC_UDCICR1_IESOF		( 0x1U << 30 )  // Interrupt Enable - SOF
#define XLLP_UDC_UDCICR1_IECC		( 0x1U << 31 )  // Interrupt Enable - Configuration Change

#define XLLP_UDC_UDCICR1_EVENTS     ( 0x1FU << 27 ) // Mask to enable all event interrupts
#define XLLP_UDC_UDCICR1_ENABLE_ALL 0xFFFF          // Mask to enable all endpoint Q - X interrupts

// UDC Interrupt Status Register 0 (UDCICR0)
#define XLLP_UDC_UDCISR0_IR0_0		( 0x1U << 0 )	// Packet Complete Interrupt Request - Endpoint 0
#define XLLP_UDC_UDCISR0_IR0_1		( 0x1U << 1 )   // FIFO Error Interrupt Request - Endpoint 0
#define XLLP_UDC_UDCISR0_IRA_0		( 0x1U << 2 )	// Packet Complete Interrupt Request - Endpoint A
#define XLLP_UDC_UDCISR0_IRA_1		( 0x1U << 3 )   // FIFO Error Interrupt Request - Endpoint A
#define XLLP_UDC_UDCISR0_IRB_0		( 0x1U << 4 )	// Packet Complete Interrupt Request - Endpoint B
#define XLLP_UDC_UDCISR0_IRB_1		( 0x1U << 5 )   // FIFO Error Interrupt Request - Endpoint B
#define XLLP_UDC_UDCISR0_IRC_0		( 0x1U << 6 )	// Packet Complete Interrupt Request - Endpoint C
#define XLLP_UDC_UDCISR0_IRC_1		( 0x1U << 7 )   // FIFO Error Interrupt Request - Endpoint C
#define XLLP_UDC_UDCISR0_IRD_0		( 0x1U << 8 )	// Packet Complete Interrupt Request - Endpoint D
#define XLLP_UDC_UDCISR0_IRD_1		( 0x1U << 9 )   // FIFO Error Interrupt Request - Endpoint D
#define XLLP_UDC_UDCISR0_IRE_0		( 0x1U << 10 )	// Packet Complete Interrupt Request - Endpoint E
#define XLLP_UDC_UDCISR0_IRE_1		( 0x1U << 11 )  // FIFO Error Interrupt Request - Endpoint E
#define XLLP_UDC_UDCISR0_IRF_0		( 0x1U << 12 )	// Packet Complete Interrupt Request - Endpoint F
#define XLLP_UDC_UDCISR0_IRF_1		( 0x1U << 13 )  // FIFO Error Interrupt Request - Endpoint F
#define XLLP_UDC_UDCISR0_IRG_0		( 0x1U << 14 )	// Packet Complete Interrupt Request - Endpoint G
#define XLLP_UDC_UDCISR0_IRG_1		( 0x1U << 15 )  // FIFO Error Interrupt Request - Endpoint G
#define XLLP_UDC_UDCISR0_IRH_0		( 0x1U << 16 )	// Packet Complete Interrupt Request - Endpoint H
#define XLLP_UDC_UDCISR0_IRH_1		( 0x1U << 17 )  // FIFO Error Interrupt Request - Endpoint H
#define XLLP_UDC_UDCISR0_IRI_0		( 0x1U << 18 )	// Packet Complete Interrupt Request - Endpoint I
#define XLLP_UDC_UDCISR0_IRI_1		( 0x1U << 19 )  // FIFO Error Interrupt Request - Endpoint I
#define XLLP_UDC_UDCISR0_IRJ_0		( 0x1U << 20 )	// Packet Complete Interrupt Request - Endpoint J
#define XLLP_UDC_UDCISR0_IRJ_1		( 0x1U << 21 )  // FIFO Error Interrupt Request - Endpoint J
#define XLLP_UDC_UDCISR0_IRK_0		( 0x1U << 22 )	// Packet Complete Interrupt Request - Endpoint K
#define XLLP_UDC_UDCISR0_IRK_1		( 0x1U << 23 )  // FIFO Error Interrupt Request - Endpoint K
#define XLLP_UDC_UDCISR0_IRL_0		( 0x1U << 24 )	// Packet Complete Interrupt Request - Endpoint L
#define XLLP_UDC_UDCISR0_IRL_1		( 0x1U << 25 )  // FIFO Error Interrupt Request - Endpoint L
#define XLLP_UDC_UDCISR0_IRM_0		( 0x1U << 26 )	// Packet Complete Interrupt Request - Endpoint M
#define XLLP_UDC_UDCISR0_IRM_1		( 0x1U << 27 )  // FIFO Error Interrupt Request - Endpoint M
#define XLLP_UDC_UDCISR0_IRN_0		( 0x1U << 28 )	// Packet Complete Interrupt Request - Endpoint N
#define XLLP_UDC_UDCISR0_IRN_1		( 0x1U << 29 )  // FIFO Error Interrupt Request - Endpoint N
#define XLLP_UDC_UDCISR0_IRP_0		( 0x1U << 30 )	// Packet Complete Interrupt Request - Endpoint P
#define XLLP_UDC_UDCISR0_IRP_1		( 0x1U << 31 )  // FIFO Error Interrupt Request - Endpoint P

// UDC Interrupt Status Register 1 (UDCICR1)
#define XLLP_UDC_UDCISR1_IRQ_0		( 0x1U << 0 )	// Packet Complete Interrupt Request - Endpoint Q
#define XLLP_UDC_UDCISR1_IRQ_1		( 0x1U << 1 )   // FIFO Error Interrupt Request - Endpoint Q
#define XLLP_UDC_UDCISR1_IRR_0		( 0x1U << 2 )	// Packet Complete Interrupt Request - Endpoint R
#define XLLP_UDC_UDCISR1_IRR_1		( 0x1U << 3 )   // FIFO Error Interrupt Request - Endpoint R
#define XLLP_UDC_UDCISR1_IRS_0		( 0x1U << 4 )	// Packet Complete Interrupt Request - Endpoint S
#define XLLP_UDC_UDCISR1_IRS_1		( 0x1U << 5 )   // FIFO Error Interrupt Request - Endpoint S
#define XLLP_UDC_UDCISR1_IRT_0		( 0x1U << 6 )	// Packet Complete Interrupt Request - Endpoint T
#define XLLP_UDC_UDCISR1_IRT_1		( 0x1U << 7 )   // FIFO Error Interrupt Request - Endpoint T
#define XLLP_UDC_UDCISR1_IRU_0		( 0x1U << 8 )	// Packet Complete Interrupt Request - Endpoint U
#define XLLP_UDC_UDCISR1_IRU_1		( 0x1U << 9 )   // FIFO Error Interrupt Request - Endpoint U
#define XLLP_UDC_UDCISR1_IRV_0		( 0x1U << 10 )	// Packet Complete Interrupt Request - Endpoint V
#define XLLP_UDC_UDCISR1_IRV_1		( 0x1U << 11 )  // FIFO Error Interrupt Request - Endpoint V
#define XLLP_UDC_UDCISR1_IRW_0		( 0x1U << 12 )	// Packet Complete Interrupt Request - Endpoint W
#define XLLP_UDC_UDCISR1_IRW_1		( 0x1U << 13 )  // FIFO Error Interrupt Request - Endpoint W
#define XLLP_UDC_UDCISR1_IRX_0		( 0x1U << 14 )	// Packet Complete Interrupt Request - Endpoint X
#define XLLP_UDC_UDCISR1_IRX_1		( 0x1U << 15 )  // FIFO Error Interrupt Request - Endpoint X
#define XLLP_UDC_UDCISR1_IRRS		( 0x1U << 27 )  // Interrupt Request - Reset
#define XLLP_UDC_UDCISR1_IRSU		( 0x1U << 28 )  // Interrupt Request - Suspend
#define XLLP_UDC_UDCISR1_IRRU		( 0x1U << 29 )  // Interrupt Request - Resume
#define XLLP_UDC_UDCISR1_IRSOF		( 0x1U << 30 )  // Interrupt Request - SOF
#define XLLP_UDC_UDCISR1_IRCC		( 0x1U << 31 )  // Interrupt Request - Configuration Change

#define XLLP_UDC_UDCISR1_EVENTS     ( 0x1FU << 27 ) // Mask to clear all event interrupts

// UDC Endpoint 0 Control/Status Register (UDCCSR0)
#define XLLP_UDC_UDCCSR0_OPR		( 0x1U << 0 )	// OUT packet to endpoint zero received
#define XLLP_UDC_UDCCSR0_IPR		( 0x1U << 1 )	// Packet has been written to endpoint zero FIFO
#define XLLP_UDC_UDCCSR0_FTF		( 0x1U << 2 )	// Flush the Tx FIFO
#define XLLP_UDC_UDCCSR0_SST		( 0x1U << 4 )	// UDC sent stall handshake
#define XLLP_UDC_UDCCSR0_FST		( 0x1U << 5 )	// Force the UDC to issue a stall handshake
#define XLLP_UDC_UDCCSR0_RNE		( 0x1U << 6 )	// There is unread data in the Rx FIFO
#define XLLP_UDC_UDCCSR0_SA			( 0x1U << 7 )	// Current packet in FIFO is part of UDC setup command

// UDC Endpoint Control/Status Registers A-X
#define XLLP_UDC_UDCCSR_FS			( 0x1U << 0 )	// FIFO needs service
#define XLLP_UDC_UDCCSR_PC			( 0x1U << 1 )	// Packet Complete
#define XLLP_UDC_UDCCSR_TRN			( 0x1U << 2 )	// Endpoint FIFO error
#define XLLP_UDC_UDCCSR_DME			( 0x1U << 3 )	// DMA Enable
#define XLLP_UDC_UDCCSR_SST			( 0x1U << 4 )	// Sent STALL
#define XLLP_UDC_UDCCSR_FST			( 0x1U << 5 )	// Force STALL
#define XLLP_UDC_UDCCSR_BNE_BNF		( 0x1U << 6 )	// Buffer not empty/full
#define XLLP_UDC_UDCCSR_SP			( 0x1U << 7 )	// Short Packet
#define XLLP_UDC_UDCCSR_FEF			( 0x1U << 8 )	// Flash Endpoint FIFO
#define XLLP_UDC_UDCCSR_DPE			( 0x1U << 9 )	// Data Packet Error

// UDC Endpoint A-X Configuration Registers
#define XLLP_UDC_UDCCRZ_EE			( 0x1U << 0 )	// Endpoint Enable
#define XLLP_UDC_UDCCRZ_DE_SHIFT    1
#define XLLP_UDC_UDCCRZ_DE			( 0x1U << 1 )	// Double-buffering Enable
#define XLLP_UDC_UDCCRZ_MPS_SHIFT	2
#define XLLP_UDC_UDCCRZ_MPS_MASK    ( 0x3FFU << XLLP_UDC_UDCCRZ_MPS_SHIFT) // Maximum Packet Size
#define XLLP_UDC_UDCCRZ_ED_SHIFT    12
#define XLLP_UDC_UDCCRZ_ED			( 0x1U << 12 )	// Endpoint Direction
#define XLLP_UDC_UDCCRZ_ET_SHIFT    13
#define XLLP_UDC_UDCCRZ_ET_MASK     ( 0x3U << XLLP_UDC_UDCCRZ_ET_SHIFT)  // Endoint Type
#define XLLP_UDC_UDCCRZ_EN_SHIFT    15
#define XLLP_UDC_UDCCRZ_EN_MASK     ( 0xFU << XLLP_UDC_UDCCRZ_EN_SHIFT)  // Endoint Number
#define XLLP_UDC_UDCCRZ_AISN_SHIFT  19
#define XLLP_UDC_UDCCRZ_AISN_MASK   ( 0x7U << XLLP_UDC_UDCCRZ_AISN_SHIFT)  // Interface Alternate Settings Number
#define XLLP_UDC_UDCCRZ_IN_SHIFT    22
#define XLLP_UDC_UDCCRZ_IN_MASK     ( 0x7U << XLLP_UDC_UDCCRZ_IN_SHIFT)    // Interface Number
#define XLLP_UDC_UDCCRZ_CN_SHIFT    25
#define XLLP_UDC_UDCCRZ_CN_MASK     ( 0x3U << XLLP_UDC_UDCCRZ_CN_SHIFT)    // Configuration Number

//
// UDC Control Register Macros (UDCCR)
//
#define UDC_CR( p ) ((PSER_INFO) p)->pUDCRegs->udc_cr

// UDC Enable (UDE)
//Mask for write 1 to clear bits in UDCCR
#define UDCCR_MASK                    (XLLP_UDC_UDCCR_EMCE)
#define UDCCR_MWRITE( pUDCCR, y )	  ((pUDCCR) = (((pUDCCR) & (~UDCCR_MASK)) | y))

//Enable UDC
#define UDCCR_UDE_ENABLE(pUDCCR)      (UDCCR_MWRITE(pUDCCR, XLLP_UDC_UDCCR_UDE))
//Disable UDC
#define UDCCR_UDE_DISABLE(pUDCCR)     ((pUDCCR) = ((pUDCCR) & (~(UDCCR_MASK | XLLP_UDC_UDCCR_UDE))))

//Force UDC out of suspend
#define UDCCR_UDR_FORCE_RESUME(pUDCCR)      (UDCCR_MWRITE(pUDCCR, XLLP_UDC_UDCCR_UDR))
//Maintain UDC suspend state
#define UDCCR_UDR_MAINTAIN_SUSPEND(pUDCCR)     ((pUDCCR) = ((pUDCCR) & (~(UDCCR_MASK | XLLP_UDC_UDCCR_UDR))))

//Clear the Endpoint Memory Configuration Error (write 1 to clear)
#define UDCCR_EMCE_CLR(pUDCCR)     (UDCCR_MWRITE(pUDCCR, XLLP_UDC_UDCCR_EMCE))

//Switch Endpoint Memory to Active Configuration
#define UDCCR_SMAC_SET(pUDCCR)     (UDCCR_MWRITE(pUDCCR, XLLP_UDC_UDCCR_SMAC))

//Set   UDCCR bit
//#define  UDCCR_SET_BIT(pUDCCR, y )     ( UDCCR_MWRITE(pUDCCR, (y)) )
//Clear UDCCR bit
//#define UDCCR_CLEAR_BIT(pUDCCR, y)     ( (pUDCCR) = ((pUDCCR) & (~(UDCCR_MASK | (y)))) )

//Define Register mask REG_MASK
//#define REG_MASK (x)
//Set Register Bit
//#define  REG_SET_BIT(pReg, y )     ((pReg) = (((pReg) & (~REG_MASK))  | (y)) )  //( UDCCR_MWRITE(pUDCCR, (y)) )
//Clear reg bit
//#define REG_CLEAR_BIT(pReg, y)     ((pReg) = ((pReg) &  (~(REG_MASK | (y)))) )


//
// UDC Interrupt Control Register 0 (UDCICR0) Macros
//
#define UDC_ICR0( p ) ((PSER_INFO) p)->pUDCRegs->udc_icr0

#define UDCICR0_INT_EN(pUDCICR0,x)     (pUDCICR0 |= (x))
#define UDCICR0_INT_DIS(pUDCICR0,x)    (pUDCICR0 &= ~(x))

//Enable endpoint interrupt
#define ENABLE_EP_INTR_FIFO_ERROR(p,x)               (UDC_ICR0(p) |=  (x))
#define ENABLE_EP_INTR_PKT_COMPLETE(p,x)             (UDC_ICR0(p) |=  (x))
#define ENABLE_EP_INTR_FIFO_ERROR_PKT_COMPLETE(p,x)  (UDC_ICR0(p) |=  (x))
#define DISABLE_EP_INTR_FIFO_ERROR(p,x)              (UDC_ICR0(p) &= ~(x))
#define DISABLE_EP_INTR_PKT_COMPLETE(p,x)            (UDC_ICR0(p) &= ~(x))
#define DISABLE_EP_INTR_FIFO_ERROR_PKT_COMPLETE(p,x) (UDC_ICR0(p) &= ~(x))

// Enable Endpoints 0, 1, 2 interrupts
//

//
// UDC Interrupt Control Register 1 (UDCICR1) Macros
//
#define UDC_ICR1( p ) ((PSER_INFO) p)->pUDCRegs->udc_icr1

#define UDCICR1_INT_EN(pUDCICR1,x)             (pUDCICR1 |= (x))
#define UDCICR1_INT_DIS(pUDCICR1,x)            (pUDCICR1 &= ~(x))

#define ENABLE_RESET_INTR(pUDCICR1)            (pUDCICR1 |=  (XLLP_UDC_UDCISR1_IRRS))
#define DISABLE_RESET_INTR(pUDCICR1)           (pUDCICR1 &= ~(XLLP_UDC_UDCISR1_IRRS))

#define ENABLE_SUSPEND_INTR(pUDCICR1)          (pUDCICR1 |=  (XLLP_UDC_UDCISR1_IRSU))
#define DISABLE_SUSPEND_INTR(pUDCICR1)         (pUDCICR1 &= ~(XLLP_UDC_UDCISR1_IRSU))

#define ENABLE_RESUME_INTR(pUDCICR1)           (pUDCICR1 |=  (XLLP_UDC_UDCISR1_IRRU))
#define DISABLE_RESUME_INTR(pUDCICR1)          (pUDCICR1 &= ~(XLLP_UDC_UDCISR1_IRRU))

#define ENABLE_START_OF_FRAME_INTR(pUDCICR1)   (pUDCICR1 |=  (XLLP_UDC_UDCISR1_IRSOF))
#define DISABLE_START_OF_FRAME_INTR(pUDCICR1)  (pUDCICR1 &= ~(XLLP_UDC_UDCISR1_IRSOF))

#define ENABLE_CONFIG_CHANGE_INTR(pUDCICR1)    (pUDCICR1 |=  (XLLP_UDC_UDCISR1_IRCC))
#define DISABLE_CONFIG_CHANGE_INTR(pUDCICR1)   (pUDCICR1 &= ~(XLLP_UDC_UDCISR1_IRCC))


//
// UDC Interrupt Status Register 0 (UDCISR0) Macros
//
#define UDC_ISR0( p ) ((PSER_INFO) p)->pUDCRegs->udc_isr0
// Mask for write 1 to clear bits in UDCCS0
#define UDCISR0_MASK  (0xFF)
#define UDCISR0_MWRITE( pUDCISR0, y )  (pUDCISR0 = ((pUDCISR0 & (~UDCISR0_MASK)) | y))

//Clear endpoint interrupt
#define UDC_ISR0_CLEAR_ENDPOINT_INTR(pUDCISR0, y)  UDCISR0_MWRITE( pUDCISR0, (y))


//
// UDC Interrupt Status Register 1 (UDCISR1) Macros
//

#define UDC_ISR1( p ) ((PSER_INFO) p)->pUDCRegs->udc_isr1

// Mask for write 1 to clear bits in UDCCS1
#define UDCISR1_MASK  (0xFF)
//#define UDCISR1_MWRITE( pUDCISR1, y )  (pUDCISR1 = ((UDCISR1(pUDCISR1) & (~UDCISR1_MASK)) | y))
#define UDCISR1_MWRITE( pUDCISR1, y )    (pUDCISR1 = (y))

//Clear endpoint interrupt
#define UDCISR1_CLEAR_ENDPOINT_INTR(pUDCISR1, y)  UDCISR1_MWRITE( pUDCISR1, (y))

#define CLEAR_RESET_INTR(pUDCISR1)            UDCISR1_MWRITE( pUDCISR1, XLLP_UDC_UDCISR1_IRRS)
#define CLEAR_SUSPEND_INTR(pUDCISR1)          UDCISR1_MWRITE( pUDCISR1, XLLP_UDC_UDCISR1_IRSU)
#define CLEAR_RESUME_INTR(pUDCISR1)           UDCISR1_MWRITE( pUDCISR1, XLLP_UDC_UDCISR1_IRRU)
#define CLEAR_START_OF_FRAME_INTR(pUDCISR1)   UDCISR1_MWRITE( pUDCISR1, XLLP_UDC_UDCISR1_IRSOF)
#define CLEAR_CONFIG_CHANGE_INTR(pUDCISR1)    UDCISR1_MWRITE( pUDCISR1, XLLP_UDC_UDCISR1_IRCC)

//
// UDC Frame Number Register (UDCFNR) Macros
//
#define UDC_FNR( p ) ((PSER_INFO) p)->pUDCRegs->udc_fnr

//
// UDC Endpoint 0 Control/Status Register (UDCCSR0) Macros
//
#define UDC_CSR0( p ) ((PSER_INFO) p)->pUDCRegs->udc_csr0

// Mask for write 1 to clear bits in UDCCS0
#define UDCCSR0_MASK					(XLLP_UDC_UDCCSR0_SST | XLLP_UDC_UDCCSR0_OPR | XLLP_UDC_UDCCSR0_SA)
#define UDC_CSR0_MWRITE( pUDCCSR0, y )	(pUDCCSR0 = ((pUDCCSR0 & (~UDCCSR0_MASK)) | y))

//Enable DMA
#define UDC_CSR0_ENABLE_DMA(pUDCCSR0)      (UDCCR0_MWRITE(pUDCCSR0, XLLP_UDC_UDCCSR0_DME))
//Disable DMA
#define UDC_CSR0_DISABLE_DMA(pUDCCSR0)     ((pUDCCSR0) = ((pUDCCSR0) & (~(UDCCSR0_MASK | XLLP_UDC_UDCCSR0_DME))))

//
// UDC Endpoints A-X Control/Status Register (UDCCSRx) Macros
//
#define UDC_CSR_A( p ) ((PSER_INFO) p)->pUDCRegs->udc_csrA
#define UDC_CSR_B( p ) ((PSER_INFO) p)->pUDCRegs->udc_csrB
#define UDC_CSR_C( p ) ((PSER_INFO) p)->pUDCRegs->udc_csrC

// Mask for write 1 to clear bits in UDCCSRx
#define UDCCSR_MASK					    (XLLP_UDC_UDCCSR_SST | XLLP_UDC_UDCCSR_TRN | XLLP_UDC_UDCCSR_PC)
#define UDCCSR_MWRITE(pUDCCSRx, y )		(pUDCCSRx = ((pUDCCSRx & (~UDCCSR_MASK)) | y))

#define UDCCSR_SST_CLEAR(pReg)         (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_SST))
#define UDCCSR_TRN_CLEAR(pReg)         (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_TRN))
#define UDCCSR_PC_CLEAR(pReg)          (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_PC ))

#define UDCCSR_DME_SET(pReg)           (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_DME))
#define UDCCSR_DME_CLEAR(pReg)         ((pReg) = ((pReg) & (~(UDCCSR_MASK | XLLP_UDC_UDCCSR_DME))))

#define UDCCSR_FST_SET(pReg)           (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_FST))
#define UDCCSR_FST_CLEAR(pReg)         ((pReg) = ((pReg) & (~(UDCCSR_MASK | XLLP_UDC_UDCCSR_FST))))

#define UDCCSR_FLUSH_FIFO(pReg)        (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_FEF))

#define UDCCSR_SP_SET(pReg)            (UDCCSR_MWRITE(pReg, XLLP_UDC_UDCCSR_SP))

//
// UDC Byte Count Registers (UDCBCR0, UDCBCRA-UDCBCRX)
//
#define UDC_BCR_0( p )  ((PSER_INFO) p)->pUDCRegs->udc_bcr0
#define UDC_BCR_A( p )  ((PSER_INFO) p)->pUDCRegs->udc_bcrA
#define UDC_BCR_B( p )  ((PSER_INFO) p)->pUDCRegs->udc_bcrB
#define UDC_BCR_C( p )  ((PSER_INFO) p)->pUDCRegs->udc_bcrC

//
// UDC Data Registers UDCDR0, UDCDRA-UDCDRX)
//
#define UDC_DR_0( p )  ((PSER_INFO) p)->pUDCRegs->udc_dr0
#define UDC_DR_A( p )  ((PSER_INFO) p)->pUDCRegs->udc_drA
#define UDC_DR_B( p )  ((PSER_INFO) p)->pUDCRegs->udc_drB
#define UDC_DR_C( p )  ((PSER_INFO) p)->pUDCRegs->udc_drC

//
// UDC Endpoints A-X Configuration Register (UDCCRZ) Macros
//
#define ENDPOINT_A( p ) ((PSER_INFO) p)->pUDCRegs->udc_crA
#define ENDPOINT_B( p ) ((PSER_INFO) p)->pUDCRegs->udc_crB
#define ENDPOINT_C( p ) ((PSER_INFO) p)->pUDCRegs->udc_crC

#define ENDPOINT_ENABLE(pUDCCRz,x)      (pUDCCRz |=  (XLLP_UDC_UDCCRZ_EE))
#define ENDPOINT_DISABLE(pUDCCRz,x)     (pUDCCRz &= ~(XLLP_UDC_UDCCRZ_EE))

#define DOUBLE_BUFFER_ENABLE(pUDCCRz,x)      (pUDCCRz |=  (XLLP_UDC_UDCCRZ_DE))
#define DOUBLE_BUFFER_DISABLE(pUDCCRz,x)     (pUDCCRz &= ~(XLLP_UDC_UDCCRZ_DE))

//#define XLLP_UDC_UDCCRZ_MPS_SHIFT 2
#define MAX_PKT_IN        (0x40 << 2)
#define MAX_PKT_BULK_8    (0x8  << 2)
#define MAX_PKT_BULK_16   (0x10 << 2)
#define MAX_PKT_BULK_32   (0x20 << 2)
#define MAX_PKT_BULK_64   (0x40 << 2)
#define MAX_PKT_ISO      (0x3FF << 2)

//#define XLLP_UDC_UDCCRZ_ED_SHIFT    12
#define EP_DIRECTION_IN   (0x1 << 12)
#define EP_DIRECTION_OUT  (0x0 << 12)

//#define XLLP_UDC_UDCCRZ_ET_SHIFT    13
#define EP_TYPE_INTERRUPT (0x3 << 13)
#define EP_TYPE_BULK      (0x2 << 13)
#define EP_TYPE_ISO       (0x1 << 13)

//Endpoints 1 - 15
//#define XLLP_UDC_UDCCRZ_EN_SHIFT    15
#define EP_NUM_1   (0x1  << 15)
#define EP_NUM_2   (0x2  << 15)
#define EP_NUM_3   (0x3  << 15)
#define EP_NUM_4   (0x4  << 15)
#define EP_NUM_5   (0x5  << 15)
#define EP_NUM_6   (0x6  << 15)
#define EP_NUM_7   (0x7  << 15)
#define EP_NUM_8   (0x8  << 15)
#define EP_NUM_9   (0x9  << 15)
#define EP_NUM_10  (0x10 << 15)
#define EP_NUM_11  (0x11 << 15)
#define EP_NUM_12  (0x12 << 15)
#define EP_NUM_13  (0x13 << 15)
#define EP_NUM_14  (0x14 << 15)
#define EP_NUM_15  (0x15 << 15)

//Alternate Interface Settings 0 - 7
//#define XLLP_UDC_UDCCRZ_AISN_SHIFT  19
#define ALTERNATE_INTERFACE_SETTING_0  (0x0 << 19)
#define ALTERNATE_INTERFACE_SETTING_1  (0x1 << 19)
#define ALTERNATE_INTERFACE_SETTING_2  (0x2 << 19)
#define ALTERNATE_INTERFACE_SETTING_3  (0x3 << 19)
#define ALTERNATE_INTERFACE_SETTING_4  (0x4 << 19)
#define ALTERNATE_INTERFACE_SETTING_5  (0x5 << 19)
#define ALTERNATE_INTERFACE_SETTING_6  (0x6 << 19)
#define ALTERNATE_INTERFACE_SETTING_7  (0x7 << 19)

//Interface Settings 0 - 7
//#define XLLP_UDC_UDCCRZ_IN_SHIFT    22
#define INTERFACE_SETTING_0  (0x0 << 22)
#define INTERFACE_SETTING_1  (0x1 << 22)
#define INTERFACE_SETTING_2  (0x2 << 22)
#define INTERFACE_SETTING_3  (0x3 << 22)
#define INTERFACE_SETTING_4  (0x4 << 22)
#define INTERFACE_SETTING_5  (0x5 << 22)
#define INTERFACE_SETTING_6  (0x6 << 22)
#define INTERFACE_SETTING_7  (0x7 << 22)

//Configuration Number 1-3
//#define XLLP_UDC_UDCCRZ_CN_SHIFT    25
#define CONFIG_NUM_1  (0x1 << 25)
#define CONFIG_NUM_2  (0x2 << 25)
#define CONFIG_NUM_3  (0x3 << 25)

//#define EPA  (MAX_PKT_BULK | EP_DIRECTION_IN | EP_TYPE_BULK_64 |
//              ALTERNATE_INTERFACE_SETTING_0 | INTERFACE_SETTING_0 | CONFIG_NUM_1 )

#endif

